prelim handouts corlang

How to Fetch/Read Data or Instruction from MM

Von Neumann architecture requires that all programs together with data must be stored in main memory during execution. In the case of the processor, it should have a way to read or fetch the program to be executed from the main memory. Programs cannot be executed in the main memory because it is merely a storage device and does not have circuits that can process data as what processor can do.

In order to fetch/read an instruction or data from main memory:

1. The CPU first sends the address of the memory location to be read.

2. The CPU then issues or sends the read signal to the memory.

A control signal is needed in order to fetch the data from the main memory. The read signal that is generated by the control unit indicates the type of operation that is to be performed in the main memory. This operation makes a copy of the content of the given memory address.

3. The word is then read out of memory and is loaded into a CPU internal register.

How to Write/Store Data into MM

During the execution of an instruction or program, there are instances that data or operand needs to be stored into the main memory. How does the processor determine the location in the main memory where data is to be stored?

In order to store/write data into main memory:

1. The CPU first sends the address of the memory location to be written.

In writing data into the main memory, it is necessary that the location in the main memory where data is to be stored should be identified first.

2. The CPU then sends the write signal together with the data or word to be written to memory.

The write signal is generated by the control unit and it indicates a write operation. In this operation, the current content of the location will be lost.

Example 1

Example of a typical assembly language instruction:

MOV R0, LOCA

The above instruction is an assembly language data transfer instruction. Copy the contents at memory location LOCA into a register in the processor, R0. The source address is LOCA which is a location in the main memory. Memory locations are usually named in this manner. The destination address is R0 which is a register in the processor. For the purpose of discussion, all register names is preceded by letter R and a number.

The given instruction requires the performance of several steps:

1. The instruction must be transferred or fetched from the MM into the CPU.

2. The operand at LOCA must be fetched.

3. The operand is stored in register R0.

Example 2

Take a look at another example of a typical assembly language instruction:

ADD R0, LOCA

Add the operand at memory location LOCA to the operand in a register in the processor, R0 and place the result into register R0. This instruction adds two numbers one from the main memory and one from a register in the processor. This instruction requires the ALU for the addition process.

The given instruction requires the performance of several steps:

1. The instruction must be transferred or fetched from the MM into the CPU.

2. The operand at LOCA must be fetched and added to the contents of R0.

3. The resultant sum is stored in register R0.

Connections between the Processor and the MM

The PC (Program Counter) contains the memory address of the instruction to be executed. During execution, the contents of the PC are updated to point to the next instruction.

Every time that an instruction is to be executed, the program counter releases its contents to the internal bus and sends it to the memory address register.

The MAR (Memory Address Register) holds the address of the location to or from which data are to be transferred.

As can be seen from the figure above, the connection of the MAR to the main memory is one-way or unidirectional.

The MDR (Memory Data Register) contains the data to be written or read out of the addressed location.

During the fetch operation, the MDR contains the instruction to be executed or data needed during execution. In write operation, MDR contains the data to be written into the main memory.

The IR (Instruction Register) contains the instruction that is being executed.

Before the IR executes the instruction it needs to be decoded first. As soon as the content of the MDR is transferred to the IR, the decoding process commences. After decoding, execution of the instruction will take place.

Operating Steps

1. PC is set to point to the first instruction of the program (the operating system loads the memory address of the first instruction).

2. The contents of the PC are transferred to the MAR (which is automatically transmitted to the MM) and a Read signal is sent to the MM.

3. The addressed word is read out of MM and loaded into the MDR.

4. The contents of MDR are transferred to the IR. The instruction is ready to be decoded and executed.

5. During execution, the contents of the PC are incremented or updated to point to the next instruction.

If operand or data needed by the instruction resides in MM:

1. It will have to be fetched by sending its address to the MAR and initiating a read cycle.

2. When the operand has been read from MM into the MDR, it may be transferred from the MDR to the ALU.

If result is to be stored in MM:

1. The result is sent to the MDR.

2. The address of the location where the result is to be stored is sent to the MDR and a write cycle is initiated.

Example

Enumerate the different steps needed to execute the machine instruction

ADD LOCA, R0

Assume that the instruction itself is stored in the main memory at location INSTR, and that this address is initially in register PC. The first two steps might be expressed as:

1. Transfer the contents of register PC to register MAR.

2. Issue a READ command to the main memory, and then wait until it has transferred the requested word into register MDR.

CPU Instruction Execution Steps

Instruction execution in a CPU can now be summarized by the following steps:

1. Fetching the instruction from the memory into the instruction register.

2. Incrementing the PC to point to the next instruction to be executed.

3. Determining the type of instruction fetched (instruction decoding).

4. Determining the location of data in the memory. If the instruction uses data.

5. Fetching the required data into internal CPU registers.

6. Executing the instruction.

7. Storing the results in the designated locations.

8. Return to Step 1.

This is commonly referred to as the fetch-decode-execute cycle.

Bus Structure

A bus is a collection of wires that connect several devices within a computer system.

When a word of data is transferred between units, all its bits are transferred in parallel.

A computer must have some lines for addressing and control purposes.

Three main groupings of lines:

1. Data Bus. This is for the transmission of data.

2. Address Bus. This specifies the location of data in MM.

3. Control Bus. This indicates the direction of data transfer and coordinates the timing of events during the transfer

Single Bus Structure

All units are connected to a single bus, so it provides the sole means of interconnection.

Single bus structure has advantages of simplicity and low cost. Single bus structure has disadvantages of limited speed since usually only two units can participate in a data transfer at any one time. This means that an arbitration system is required and that units will be forced to wait. (This requires Time Domain Multiplexing or TDM, the transmission of different types of information on the same lines, but at different times.)

Only two units can actively use the bus at any given time.

Bus control lines are used to arbitrate multiple requests for the use of the bus.

Buffer Registers are used to hold information during transfers. These prevent a high-speed processor from being locked to a slow I/O device during a sequence of data transfers.

Two-Bus Structure

In the first configuration, the processor is placed between the I/O unit and the memory unit. The processor is responsible for any data transfer between the I/O unit and the memory unit. The processor acts as a “messenger.” In this structure, the processor performance and capability is not being maximized. Most of the time, the processor is doing data transfer between these units instead of performing more complex applications. Also, the processor is idle most of the time waiting for these slow devices.

In the second configuration, I/O transfers are made directly to or from the memory. A special purpose processor called peripheral processor or I/O channel is needed as part of the I/O equipment to control and facilitate such transfers. This special processor for the main memory is the direct memory access (DMA) controller. It allows main memory to perform data transfer between I/O units.

Memory Locations and Addresses

MM is organized so that a group of n bits can be stored or retrieved in a single basic operation.

The M addresses constitute the address space of the computer system.

Example: For the Intel 8088/86 Microprocessor

Address Space = 1,048,576 addresses or memory locations using binary encoding of addresses, 20 bits are needed to represent all addresses, 220 = 1,048,576

Parts of an Instruction

The contents of memory locations can represent either:

1. instructions

2. operands or data (numbers or characters)

An instruction usually contains two parts:

1. the part that specifies the operation to be performed (op-code field).

2. the part that may be used to specify operand addresses.

Examples:

1. 32-bit instruction

8 bits                                      24 bits

Operation Field                    Addressing Information

2. 16-bit instruction (8088/86)

10001011 11101100

MOV SP TO BP

Main Memory Operations

Fetch or Read. This transfers the contents of a specific MM location to the CPU. The word in the MM remains unchanged.

Read/Fetch Cycle:

1. CPU sends address of the desired location.

2. MM reads the data stored at that address and sends it to the CPU.

Store or Write. This transfers a word of information from the CPU to a specific MM location. This destroys the former contents of that location.

Write/Store Cycle:

1. CPU sends address of the desired location to the MM, together with the data to be stored into that location.

2. Data is written at desired location.

Instructions and Instructions Sequencing

Types of Instructions:

1. Data transfers between MM and CPU registers.

2. Arithmetic and logic operations on data.

3. Program sequencing and control.

4. I/O operations or transfers.

Notations

R1 ß [LOC]

The contents of memory location LOC are transferred into register R1.

C  ß [A] + [B]

The operands in memory locations A and B are fetched from MM and transferred into the CPU, where they will be added in the ALU. Then the resulting sum is to be stored into memory location C in MM

Address Notations

Three-Address Instructions

ADD A, B, C            A ß [B] + [C]

B and C = source operands

A = destination operands

- The operands in memory locations B and C are fetched from MM and transferred into the CPU, where they will be added in the ALU. Then the resulting sum is to be stored into memory location A in MM.

Two-Address Instructions

ADD A, B                A ß [A] + [B]

- The operands in memory locations A and B are fetched from MM and transferred into the CPU, where they will be added in the ALU. Then the resulting sum is to be stored into memory location A in MM.

MOVE B, C             B ß [C]

- The contents of memory location C are transferred into memory location B in MM.

A common convention used is to write two-operand instructions in the form:

operation destination, source

One-Address Notation

Since addition is a two-operand operation, an implicit assumption must be made regarding the location of one of the operands as well as the result.

A general purpose CPU register, usually called the accumulator, may be used for this purpose.

Examples:

ADD A                    ACC ß [A] + [ACC]

Add the contents of memory location A to the contents of the accumulator and place the sum into the accumulator.

LOAD A ACC ß [A]

Move the contents of memory location A into the accumulator.

STORE A                 A ß [ACC]

Move the contents of memory location A into the accumulator.

Examples

LOAD A  ACC ß [A]

ADD B                     ACC ß [B] + [ACC]

STORE C                 C ß [ACC]

Zero-Address Instructions

Instructions where the locations of all operands are defined implicitly.

 Example:

 Inc (increment the accumulator by 1)

 Dec (decrement the accumulator by 1)

Two-Phase Procedure in Instruction Execution

Instruction Fetch

Instruction is fetched from MM location whose address is in the program counter. The instruction is then placed in the instruction register in the CPU.

Instruction Execute

The instruction in the instruction register is examined to determine which operation is to be performed. The CPU then performs the specified operation.

Instruction Execution and Straight-Line Sequencing

To begin the execution of this program, the address of its first instruction (i) must be placed into the PC.

The CPU control circuits automatically proceed to fetch and execute instructions, one at a time, in the order of increasing addresses. This is straight-line sequencing.

This program will add a list of n numbers. The addresses of the memory locations containing the n numbers are symbolically given as NUM1, NUM2, . . ., NUMn, and the resulting sum is placed in memory location SUM.

Branching

The fundamental idea in program loops is to cause a straight-line sequence of instructions to be executed repeatedly.

GENERALIZATION: o Control signal is needed in order to fetch the data from the main memory. o A bus is a collection of wires that connect several devices within a computer system. o Bus control lines are used to arbitrate multiple requests for the use of the bus. o Buffer registers are used to hold information during transfers. o The processor acts as a “messenger” in Two-Bus Structure.

REFERENCES: o Tanenbaum, Andrew S., (2005), Structured computer organization, Prentice Hall o Hamacher, V. C., (2002), Computer organization (5th ed.), McGraw Hill o Stallings, William, (2009), Computer organization and architecture : designing for performance (8th ed.), Prentice-Hall International o Carpinelli, John D., (2001), Computer systems organization & architecture, Addison-Wesley o Berger, Arnold S., (2005), Hardware and computer organization : the software perspective, Amsterdam : Elsevier/Newnes